The present invention relates to a semiconductor device having an integrated injection logic (IIL) cell structure, and a method of fabricating the same.
The integrated injection logic, which is often referred to as xe2x80x9cI2Lxe2x80x9d, cell comprises a common semiconductor substrate, a constant current source transistor, and a switch transistor, both of the constant current source transistor and the switch transistor being formed on the above common semiconductor substrate. The most specific feature of the I2L cell lies in that a logic circuit can be easily incorporated therein with high density by the same processing as that of bipolar transistors. The I2L cells have been widely used before CMOS (complementary MOS insulating gate field-effect transistor integrated circuit) became widespread.
At present, as the circuit element is made large-scale, high-speed, low in power consumption, and inexpensive much more by microminiaturization based on CMOS, it is frequently observed that CMOS plays a leading part in forming logic circuits.
On the other hand, the I2L cell structure makes it possible to make a linear circuit in the form of semiconductor chip. In a small or middle scale manufacturing process, the I2L cell structure is inexpensive, and hence used in commercial sector.
Logic circuits based on the I2L cell structure also can be made large-scale, high-speed, low in power consumption, and inexpensive by microminiaturization of circuit element similarly to the CMOS.
In the I2L cell structure, as a means for realizing the microminiaturization of circuit element, it is considered that structure and manufacturing method of emitter/base self-align structure bipolar transistor based on upper and lower two layers of polycrystalline silicon are applied to the I2L cell structure (see T. H. Ning, Symp. of VLSITECH, Invited Paper, Page 34 (1981)).
The logic circuit based on the I2L cell structure includes a multi-collector structure composed of a plurality of collector regions and collector electrodes formed within the unit cell. However, in this I2L cell, switching speeds are different at every collectors composing the multi-collector structure. As a consequence, a designing of circuit becomes difficult, and such logic circuit has not yet been made large-scale.
Switching speeds can be different at every collector in the above multi-collector structure. That is, a base series resistance RB is increased as the position of the collector becomes distant from the base, and a current amplification factor and a cutoff frequency at a switching transistor (bipolar transistor in the reverse direction) provided within the I2L cell structure are lowered when a potential drop occurs at that portion, resulting in the switching speed being lowered.
FIG. 1A is a plan view of a unit cell of conventional I2L cell structure, and FIG. 1B is a cross-sectional view thereof.
In this example, as illustrated in FIGS. 1A and 1B, on an n-type emitter region 60 surrounded by an emitter electrode deriving region 60a heavily doped with n-type impurity, there is formed a base region 61 composed of a p-type intrinsic base region 61s and an external base region 61g heavily doped with p-type impurity, and an injector region 62 heavily doped with p-type impurity. A plurality of collector regions 63 heavily doped with n-type impurity are formed on the intrinsic base region 61s. 
An emitter electrode E, a base electrode B, an injector electrode I, and collector electrodes C (collector electrodes C1 through C5) are respectively formed on respective regions of the emitter electrode deriving region 60a, the external base region 61g, the injector region 62, and the collector region 63 to make an ohmic contact.
Of the above-mentioned regions, the intrinsic base region 61a, and the external base region 61g are formed by implanting ions of low impurity concentration and high impurity concentration through masks.
FIG. 2 is a graph showing a relationship between an injection current of an I2L ring type oscillator and a delay time in the I2L cell structure shown in FIGS. 1A and 1B while an ion injection dose of the external base region 61g is taken as a parameter. In the I2L ring type oscillator, unit cells of odd number are selected. In each unit cell, a base electrode and a collector electrode are connected in series to a base electrode or a collector electrode of adjacent unit cell, and an output of a final gate (base electrode or collector electrode) is oscillated as an input of the first gate, thereby measuring an oscillation frequency and a switching delay time.
A base electrode of adjacent cell and one collector electrode in a plurality of collector electrodes are sequentially connected by Al wire or the like.
Specifically, assuming that B1, B2, B3, . . . Bn are base electrodes of 1, 2, 3, . . . , nth (n is an odd number) unit cells, and that C1, C2, C3, . . . , Cn are collector electrodes, then electrodes of the same kinds are connected in such a way as in B1-B2, C2-C3, B3-B4, . . . , Cnxe2x88x921-Cn or electrodes of different kinds are connected in such a way as in B1-C2, B2-C3, B3-C4, B4-C3, . . . , Bnxe2x88x921-Cn and finally the electrodes Bn-C1 are connected in a loop-fashion, thereby forming the ring type oscillator.
In FIG. 2, the vertical axis represents a delay time (n/s), and the horizontal axis represents an injection current (xcexcA), each of which is represented by a logarithmic scale.
In FIG. 2, crosses show measured results obtained when a dose of ions implanted on the external base region 61g is 1xc3x971014 cmxe2x88x922 and a layer resistance is 500 xcexa9/xe2x96xa1, and open circles show measured results obtained when a dose of ions implanted on the external base region 61g is 2xc3x971014 cmxe2x88x922 and the layer resistance is 315 xcexa9/xe2x96xa1. Open triangles show measured results obtained when the dose of ions implanted on the external base region 61g is 3xc3x971014 cmxe2x88x922, and the layer resistance is 230 xcexa9/xe2x96xa1, and open squares show measured results obtained when the dose of ions implanted on the external base region 61g is 5xc3x971014 cmxe2x88x922 and the layer resistance is 150 xcexa9/xe2x96xa1.
When the ring type oscillator comprises a base and a collector which are disposed most closely to each other, or when a base electrode and a collector electrode disposed adjacent to this base electrode in the unit cell are used in the ring type oscillator and these electrodes are disposed at the end of the opposite side of the injector (curve group A in FIG. 2), study of FIG. 2 reveals that a delay time has no dose dependence.
On the other hand, when the ring type oscillator comprises a base electrode and a collector electrode which are disposed most distant from each other, or when the base electrode adjoins the injector and the collector disposed at the end of opposite side of the injector and the base electrode in the unit cell is used in the ring type oscillator (curve group B in FIG. 2), study of FIG. 2 reveals that a delay time is reduced as the dose is increased, i.e., operation speed is increased in the large current side where the injector current is 10 xcexcA or higher.
In general, the I2L cell is formed at the same time the bipolar transistor is formed on the same semiconductor substrate as other device.
Specifically, I2L cells based on an emitter/base self-align bipolar transistor and a collector/base self-align switch transistor are simultaneously formed by first and second semiconductor layers of polycrystalline silicon. FIG. 3A is a plan view of such I2L cell structure, and FIG. 3B is a cross-sectional view thereof.
In the unit cell of the I2L cell structure shown in the plan view of FIG. 3A, an injector I, a base B, collectors C (collectors C1 to C3) and an emitter E are formed from right in FIG. 3A, in that order.
In the cross-sectional view of FIG. 3B, an emitter buried region 32 heavily doped with impurity and an emitter buried region 33 lightly doped with impurity are formed on a p-type semiconductor substrate 31. An injector region 36, a base electrode deriving region 34 and a plurality of base regions 34g each of which is heavily doped with p-type impurity are formed on the emitter region 33, and a plurality of collector regions 35 heavily doped with n-type impurity are formed on the intrinsic base regions 34s, 34s lightly doped with p-type impurity between the respective external base regions 34g. These regions constitute the I2L cell.
Emitter electrode deriving regions 38 are formed around the cell, and isolation insulating layers 37 are formed outside the emitter electrode deriving regions 38.
In actual practice, a plurality of I2L cell are formed on the common semiconductor substrate 31 at the same time, and adjacent cells are overlapped at the positions shown by broken lines in FIGS. 3A.
In the above I2L cell, the base region 34 composed of the external base regions 34g and the intrinsic base regions 34s surrounded by the external base regions 34g are formed by the process below as shown in a cross-sectional view of FIG. 4.
Initially, an oxide insulating film 42 is formed on the surface of a semiconductor substrate, and openings are respectively formed through the insulating film 42 at its portions where a base region 34, a base electrode deriving region 34b, and an injector region 36 are formed. First semiconductor layers 41 made of polycrystalline silicon doped with p-type impurity are formed on the emitter region 33 through these openings.
Further, interlayer insulators 43 are formed over the whole surface of the first semiconductor layer 41, and openings are formed through the interlayer insulators 43 and the first semiconductor layers 41 formed under the interlayer insulators 43 at their portion where collector regions are formed. Through these openings, ions of p-type impurity are implanted on the intrinsic base region.
An insulating film 50 is formed over the whole surface by CVD (chemical vapor deposition).
Then, p-type impurities of high concentration are diffused from the first semiconductor layer 41 into the emitter region 33 by annealing, thereby forming the external base regions 34g, the base electrode deriving region 34b, and the injector region 36. Intrinsic base regions 34s are composed of the portions which are formed by implanting p type ions.
In this manner, as shown in the cross-sectional view of FIG. 4, there is formed the base region 34 composed of the intrinsic base region 34s and the external base region 34g. 
Thereafter, side walls are formed in the openings of the above collector region forming portions by etching the insulating film 50 by RIE (reactive ion etching) as shown in FIG. 3B. Then, as shown in FIG. 3B, second semiconductor layers 44 of polycrystalline silicon doped with n-type impurity are formed on the intrinsic base regions 34s over the whole collector region forming region through these openings. Subsequently, collector regions 35 are formed by diffusing n-type impurities from the second semiconductor layers 44 by annealing.
Electrode contact openings are formed on the insulating films 42 and the interlayer insulators 43 on the emitter electrode deriving region 38, and electrode contact openings for exposing the first semiconductor layers 41 are formed on the interlayer insulators 43 on the base electrode deriving regions 34b and the injector regions 36. A metal layer such as an Al layer is deposited on the whole surface, and an emitter electrode 45e, a base electrode 45b, an injector electrode 45i, and a collector electrode 45c are respectively formed on the first semiconductor layer 41 on the base electrode deriving region 34b, the first semiconductor layer 41 on the injector region 36, and the second semiconductor layer 44 on each collector region 35 by patterning based on photolithography. The second semiconductor layer 44 is etched away except the collector electrode forming portion after the collector electrode 45c has been treated by patterning.
The base region 34 and the base electrode deriving region 34b are formed by the first semiconductor layer 41, and the positions of the base region 34 and the base electrode deriving region 34b are aligned by the first semiconductor layer 41. Further, the base electrode 45b formed on the base electrode deriving region 34b in ohmic contact is electrically connected to the base regions 34. The collector regions 35 and the base regions 34 are aligned by the second semiconductor layers 44, and the collector electrode deriving regions 34b are aligned with the collector regions 35 by the second semiconductor layers 44.
In the above arrangement, the base electrode 45b and the base regions 34 are electrically coupled by the first semiconductor layers 41 formed on the insulating layer 42, and hence a resistivity of the polycrystalline silicon layer doped with impurity is relatively large. As a consequence, a resistance of bases connected in series concerning the base region distant from the base electrode 45b, in particular, is increased.
In view of the aforesaid aspect, it is an object of the present invention to provide a logic circuit with I2L cell structure in which a difference of switching speeds at every collector in a multi-collector structure is small.
According to an aspect of the present invention, there is provided a semiconductor device having an integrated injection logic cell composed of a constant current source transistor and a switch transistor formed on a common semiconductor substrate. This semiconductor device is comprised of a first semiconductor layer doped with a first conductivity type impurity, a second semiconductor layer doped with a second conductivity type impurity, the first and second semiconductor layers being formed on the semiconductor substrate such that they are electrically isolated from each other, a plurality of collector electrodes of the switch transistor being formed by the second semiconductor layer, a plurality of collector regions being formed by diffusion of impurity from the second semiconductor layer, a base electrode deriving portion formed on the first semiconductor layer, a direct contact portion being formed on the first semiconductor layer and which directly contacts with the semiconductor substrate among the collector regions, and an external base region being formed from the direct contact portion by diffusion of the first conductivity type impurity.
According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device having an integrated injection logic cell composed of a constant current source transistor and a switch transistor formed on a common semiconductor substrate. This method is comprised of the steps of forming an element separating and isolating layer on the semiconductor substrate, forming an emitter buried region of the switch transistor, forming openings on the insulating layer at its region covering a portion in which a plurality of collector regions of the switch transistors are formed and at its injection electrode deriving portion, forming a first semiconductor layer of a first conductivity type through the openings of the insulating layer so as to communicate with the semiconductor substrate, patterning the first semiconductor layer, forming a layer insulating layer over the first semiconductor layer, forming openings on the layer insulating layer at its collector region forming portions, an injection electrode deriving portion and the switch transistor emitter electrode deriving portion, forming a second semiconductor layer of a second conductivity type so as to cover the openings of said collector region forming portions of the layer insulating layer, and leaving the collector region and the collector electrode forming portion on the second semiconductor layer by patterning, wherein when the first semiconductor layer is patterned, the injection electrode, the base electrode, and a portion located between the base region forming portion and a plurality of collector regions are left.
According to the present invention, in the integrated injection logic (I2L) cell structure including the constant current source transistor and the switch transistor, with respect to the first semiconductor layer doped with the first conductivity type impurity formed on the semiconductor substrate, there are formed the base electrode deriving portion, and the direct contact portion which directly contacts with the semiconductor substrate between a plurality of collector regions. The external base region is formed by diffusion of the first conductivity type impurity from the direct contact portion, whereby external base regions with low resistance formed by the diffusion of the first conductivity type impurity are continuously formed so as to cover the base electrode deriving portion and a plurality of collector regions.
As described above, since the external base regions with low resistance are continuously formed under the base electrode deriving portion and a plurality of collector regions, a resistance between the base and the collector can be reduced.
When the first semiconductor layer is formed, the first semiconductor layer is patterned so as to leave the injection electrode, the base electrode, the base region forming portion, and a portion located between a plurality of collector regions, whereby the aforementioned direct contact portion is formed on the portion located between the base region forming portion and a plurality of collector regions. Therefore, the external base region with low resistance can be continuously formed between a plurality of collector regions by diffusing impurity from the direct contact portion.